The present invention relates to a technique of chemico-mechanically polishing a film formed on a wafer with a high thickness controllability until a prescribed thickness is reached.
Along with the recent tendency of scaledown of semiconductor devices, importance is placed on the technique for flattening the wafer surface more than ever. Among others, chemical-mechanical polishing (hereinafter referred to from time to time as “CMP”) is excellent in productivity, has many other advantages, and occupies a particularly important position among the flattening techniques. In the CMP process, it is important to accurately set conditions for obtaining a target thickness, particularly, a polishing time.
Japanese Patent Publication No. 3077656 discloses a recipe correcting method of a semiconductor device, which permits improvement of the process treatment ability without causing a change in the amount of polishing even upon a change in the polishing rate, and eliminating the necessity of re-polishing. The method disclosed in the Publication comprises the steps of monitoring the polishing rate of a semiconductor manufacturing apparatus performing chemico-mechanical polishing, calculating a polishing time from the thus monitored polishing rate and required amount of polishing, selecting process recipe information based on the calculated polishing time from a process recipe selection table as a recipe change portion, and adding the thus selected recipe change portion to a predetermined recipe fixed portion, thereby correcting the recipe information.
Methods for determining the polishing time and polishing conditions for the subsequent runs on the basis of data regarding the polishing time and the amount of polishing upon chemico-mechanically polishing a wafer are disclosed in some other patent publications.
Japanese Unexamined Patent Publication No. 10-106984 discloses a method of calculating an optimum polishing time from the polishing time, the target thickness value, and the thickness before and after polishing, and applying the thus calculated optimum polishing time to the subsequent runs of polishing. Japanese Unexamined Patent Application Publication No. 10-98016 discloses a method of detecting the status of polishing through measurement of thickness after polishing and controlling the polishing conditions from the thus measured result and a reference thickness.
Japanese Unexamined Patent Application Publication No. 8-17768 discloses a method of measuring thickness after polishing of a stepped wafer, and setting a polishing time for the next run.
In a method of determining a polishing time and polishing conditions for the subsequent runs on the basis of data regarding the polishing time and the amount of polishing as in the existing art as described above, however, determination of a optimum polishing time giving a target thickness usually requires several batches. The reason has not as yet been clarified. The present inventor therefore carried out many experiments, and clarified that the reason was the occurrence of surface irregularities on the surface of a film to be polished.
With the progress of CMP, as described above, the silicon oxide film 3 to be polished changes in shape, and the polishing rate varies with this change in condition. In the existing method of determining the polishing time, it is not taken into account that the condition of the object to be polished in response to the polishing process, and the polishing rate varies accordingly, or more specifically, that the polishing rate becomes higher in the former half of polishing because of the irregularities in shape. According to the existing method, therefore, a calculated value of polishing time tends to be shorter than the actual time. The difference between the thickness obtained upon polishing with a calculated polishing time and the target thickness is reduced by repeating batches and accumulating polishing data, and a thickness set as a target can finally be achieved. Before achieving this state, however, a number of batches are necessary. As a result, a large quantity of wafers requiring re-polishing is produced, and there occur rejectable wafers not finished into products, and a decrease in yield.